|Sample rate||6.4 GSPS|
|Input signal range||700 mVpp|
|Input bandwidth||3 GHz|
|Memory size||1024 MSamples|
|Clock||Int. / Ext. (SMA) 2 Vpp|
|Clock reference||Int. / Ext. 10 MHz / PXIe|
|Interfaces||USB 2.0 & PXIe|
The ADQ108 is an 8 bit ultra high-speed digitizer with a unique 6.4 GSPS capture rate, enabled by SP Devices’ ADC interleaving technology ADX, the ADQ108 opens for demanding wide band RF/IF sampling, high resolution ranging and high-speed data recording.
Analog Front End (AFE)
The AFE of the ADQ108 is AC-coupled and designed for optimal dynamic performance over a wide bandwidth.
Interface to the Host
The digitizer connects to the host via a high-speed USB 2.0 cable or through an optional Compact PCI Express / PXI Express interface. All interface types allows for streaming of data at high transfer rates.
Front Panel Input Terminals
Analog input: Analog input signal single ended 50 Ohms AC coupled.
External clock source: An external input for synchronized system.
External clock reference: An external 10 MHz input for synchronized system.
External trigger input: External high precision 50 Ohms terminated trigger signal with threshold 0.5 V.
External trigger output: High precision digital output for triggering other digitizers in a system.
GPIO: 5 ports, 3.3V general purpose bi-directional digital signals.
Software Development Kit (SDK)
The ADQ108 comes with an easy-to-use API that allows easy integration into any application. Software tools for application development include C/C++, Matlab and DLLs for Windows XP/Vista. The SDK also includes SP Devices´ data capture tool, ADCaptureLab.
FPGA and the ADQ Development Kit
The digital back end of the ADQ108 is a ADQ DSP board equipped with a Xilinx Virtex 6 LX240T FPGA. The FPGA runs the SP Devices’ interleaving algorithm and handles the data management, such as DRAM, host communication, triggers and control. The FPGA is opened to the user through the ADQ Development Kit for implementation of customized signal processing. The ADQ Development Kit contains everything that is needed to get started with the FPGA development, and also includes examples and documentation. FPGA upgrades are available for demanding real time signal processing tasks.
Standard trigger options are external, software and level trigger. The ADQ108 supports single and multiple records. The multiple records mode can be combined with any trigger function. A time stamp function tags each record with timing information.